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September 24-25, 2012 -- Techmart, Santa Clara, CA USA
The purposes of the IEEE Workshop on Chip-Packaging Co-Design for High Performance Electronic Systems are to provide a forum for technical education and research interchange on the topic of chip-packaging co-design, and co-design manufacturing and reliability impacts. The workshop is organized around two days of invited papers and contributed papers.
This second annual workshop is aimed at systems, signal integrity, power integrity, circuit design, and reliability engineers/managers wishing to better understand challenges and solutions in system design, manufacturing, and qualification. Attendance is limited, and the venue provides a good atmosphere for networking during the sessions, coffee breaks, and buffet lunches.
Please download our Call for Papers; submission deadline for abstracts is July 20, 2012.
Please join our IEEE ListServ Dlist to receive further information about CPCW:
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Join our Platinum, Gold and Silver Sponsors and Exhibitors -- visit our Sponsorship Page
To be added to our Distribution List for future information on CPCW, please send an email note to us: Paul Wesling.
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CPCW'11 Officers:
General Chair:
Technical Program Chair:
Technical Program Co-Chair:
CPMT Society Rep:
CPMT Society Rep:
Administrative Chair:
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